1. Field of the Invention
The present invention relates to a redundancy fuse circuit in which a defective address is programmed, particularly to a semiconductor integrated circuit including memories such as a semiconductor memory and a memory embedded microcomputer.
2. Description of the Related Art
In a semiconductor integrated circuit including memories such as a semiconductor memory and a memory embedded microcomputer, a defect is generated in a part of a memory cell at a manufacturing time by miniaturization of the memory cell, and the memory cell sometimes becomes defective. In this case, a method is used in which a redundancy fuse circuit is circuit, the defective cell is replaced with a redundancy cell, and a chip is remedied.
FIG. 1 shows an example of a memory circuit including a conventional redundancy fuse circuit.
A memory cell array 10A comprises a plurality of memory cells arranged in an array. Any type of memory cell may be used. A redundancy cell array 10B is disposed adjacent to the memory cell array 10A. The redundancy cell array 10B comprises a plurality of redundancy cells arranged in the array. The redundancy cells replace the defective cells in a case where the defective cells exist in the memory cell array 10A.
A plurality of, for example, 512 word lines are arranged in the memory cell array 10A. These word lines are blocked, for example, every eight lines, and the defective cells are replaced with the redundancy cells by a block unit.
For example, as a result of a test of the memory cell array 10A, if the defective cells are present in positions (A) and (B) in the memory cell array 10A, the defective cells are replaced with the redundancy cells by a unit of eight rows (eight word lines) in the block including the defective cells.
An address signal is input into an address decoder 12 via an address buffer 11. The address decoder 12 decodes the address signal to output a main row address signal MRA, a sub-row address signal SRA, and a column address signal CA.
The main row address signal MRA is input into a main body cell decoder 16 of a sub-row decoder 14 via a main body cell (M/C) decoder 15 of a main row decoder 13. The sub-row address signal SRA is input into the main body cell decoder 16 and a redundancy (R/D) decoder 19 of the sub-row decoder 14 via a common decoder 17 in the sub-row decoder 14. The column address signal CA is input into a column decoder 20.
For example, read data is output as output data BIT0, BIT1, . . . , BITm-1 to the outside of the chip via a column select switch 21, sense amplifies (S/A) 22, and buffers 23.
Defective addresses are programmed in fuse circuits F0, F1, . . . . Concretely, the address (n bits in the present example) of the block including the defective cells is programmed in the fuse circuits F0, F1, . . . . For example, the number of fuse circuits F0, F1, . . . is equal to that of blocks constituting a redundancy array in a memory cell array 10.
The fuse circuits F0, F1, . . . may be of a type in which the defective address is stored by presence/absence of cut-off of a fuse by laser, or an electric fuse (E-fuse) capable of electrically cutting off the fuse may also be used. The fuse circuits F0, F1, . . . are connected to an OR circuit OR1 via selectors SEL0, SEL1, . . . .
When the defective cells are present in the memory cell array 10A, the selectors SEL0, SEL1, . . . select one fuse circuit Fi based on fuse block select signals BLK0, BLK1, . . . . A selector SELi for the selected fuse circuit Fi outputs the defective address programmed in the fuse circuit Fi. The selectors for all the non-selected remaining fuse circuits set all output data of n bits to “0”.
Therefore, the defective address programmed in the selected fuse circuit Fi is input into a comparator 24 via the selector SELi and OR circuit OR1. For example, when the fuse block select signal BLK0 is “H”, and the other fuse block select signals BLK1, . . . are “L”, the defective address of n bits programmed in a fuse circuit F0 is input into the comparator 24 via the selector SEL0 and OR circuit OR1.
The comparator 24 compares n-bits external address data with defective address data of n bits output from the OR circuit OR1. When both the data disagree, for example, a flag FLAG is set to “L”. At this time, the address decoder 12 is activated to execute a usual decode operation. When the data agree with each other, for example, the comparator 24 sets the flag FLAG to “H”. At this time, the address decoder 12 is inactivated, and redundancy decoders 18, 19 of the main/sub-row decoders 13, 14 are activated.
The conventional redundancy fuse circuits have the following problems.
{circle around (1)} Even when the defective cells are replaced with the redundancy cells after a test step, the chip cannot be remedied for a reason that the redundancy cells have defects. In this case, a step of cutting off the fuse is useless, and this causes an increase of manufacturing cost.
{circle around (2)} An address different from the address in which the defective cell is present is sometimes programmed by mistake. Even in this case, the chip cannot be remedied, the step of cutting off the fuse is useless, and this causes the increase of manufacturing cost.
{circle around (3)} When the chip cannot be remedied even after the step of cutting off the fuse as described in {circle around (1)} and {circle around (2)}, this cannot be confirmed until the fuse is cut off, and the fuse cut-off step is useless. Once the fuse is cut off, the fuse cannot be returned to an original state.
If these problems can be confirmed before cutting off the fuse, the fuse cut-off step is not performed with respect to the chip whose defect cannot-be remedied, and this is effective for reduction of the manufacturing cost.
Moreover, especially since an environment for the fuse cut-off step is not sufficiently prepared in a trial stage before mass production, there is a large possibility that a cut-off defect of the fuse is caused by the influences by broken pieces, dust and the like at a fuse cut-off time. Therefore, if the operation of the redundancy fuse circuit can be confirmed without cutting off any fuse in the trial stage, this is convenient.